The continuing miniaturization of semiconductor integrated circuits has forced many conventional structures to change and has required the accompanying need to improve the processes used to create the new structures. A conventional MOS (metal oxide semiconductor) transistor gate structure for larger feature sizes, illustrated in the cross-sectional view of FIG. 1, includes highly doped source/drain (S/D) regions 10, 12 formed into a lesser doped silicon layer 14, which may be formed epitaxially over a silicon wafer or even in an silicon-on-insulator (SOI) structure. A thin gate oxide layer 16 may be formed over the entire MOS area, possibly before the implantation and anneal steps for the S/D regions 10, 12. Gate stacks 18 are formed over the gate oxide layer 16. Conventionally, the gate stacks 18 are formed by sequentially depositing a polysilicon layer 20, a tungsten silicide (WSix) layer 22, and a silicon nitride (SiN) cap layer 24. In a flash memory, an oxide-nitride-oxide (ONO) structure may be sandwiched within the polysilicon layer 20. S/D holes 26 are then photolithographically etched down to the gate oxide layer 16 over the S/D regions 10, 12 to define the stacks 18. Spacers 28, typically of silicon oxide are then formed on the sides of the stacks 18. The S/D regions 10, 12 may be implanted following the formation of the stacks 18 to use the stacks 18 as implant masks. Subsequent processing steps open the gate oxide layer 16 at the bottom of the S/D holes 26, provide an ohmic contact layer if necessary, and fill the S/D holes 26 with polysilicon or a metal to electrically contact the S/D regions 10, 12. The cap layer 24 is removed to provide electrical contact to the top of the gate oxide layer 16 between the S/D regions 10, 12 forming the MOS gate.
This structure was successfully used at the 110 nm node defined by the gate length. However, extending this design to the 90 nm mode has proven difficult. There exists a requirement for a maximum value of the sheet resistance RS of the unpatterned metal layers of the gate stacks 18, that is, the WSix layer 22 in the structure of FIG. 1. As shown by a dotted plot 30 in the graph of FIG. 2, the maximum sheet resistance RS at 90 nm is about 6 ohms per square. The sheet resistance of a layer decreases with its thickness. The WSix layer 22 for a gate length of 90 nm has a sheet resistance varying with the aspect ratio (A/R) of the patterned WSix layer 22 shown by plot 32. The aspect ratio is the ratio of the height to the width of the patterned WSix layer 22, for which the width is close to the gate length defining the node size. The graph demonstrates that an aspect ratio of at least 10 is required, which translates to a height H of the WSix layer 22 of at least 1000 nm at the 90 nm node. Such a structure is not easily manufactured.
As a result, an alternative gate structure illustrated in the cross-sectional view of FIG. 3 has been developed. Its gate stacks 40 include a tungsten nitride (WN) barrier layer 42 and a tungsten (W) via layer 44. The barrier layer 40 is required to prevent the tungsten via layer 44 from siliciding with the polysilicon layer 20. Tungsten metal is much more conductive than tungsten silicide. As a result, as illustrated by plot 46 in FIG. 2, the sheet resistance of the W/WN is much less than a corresponding thickness of WSix so that the aspect ratio, at least at 90 nm, need be no more than 1, that is, a height H of about 105 nm. Another example at the 100 nm node includes 32.5 nm of W above 7.5 nm of WN.
Sputtering is the preferred method of depositing the WN barrier layer 42 and the W via layer 44 because of the relatively inexpensive equipment and consumable target, the fast processing available, the capability to sputter both tungsten and tungsten nitride in the same sputter chamber using a tungsten target and the selective supply of nitrogen gas in depositing the nitride layer. Also, sputtered tungsten tends to demonstrate a lower resistivity and smoother surface than tungsten deposited by chemical vapor deposition (CVD).
An example of a sputter chamber 50 useful for sputtering tungsten and tungsten nitride is schematically illustrated in the cross-sectional view of FIG. 4. Such a chamber is available from Applied Materials, Inc. of Santa Clara, Calif. as the CleanW sputter chamber. The sputter chamber 50 includes a vacuum chamber 52 arranged about a central axis 54 on which a tungsten target 56 is supported through an isolator 58, which vacuum seals the target 56 to the vacuum chamber 52 and electrically isolates the target 56 from the electrically grounded vacuum chamber 52. An unillustrated vacuum pump system pumps the interior of the vacuum chamber 52 to a pressure in the low milliTorr range. At least the front surface of the tungsten target 56 is planar. The tungsten target 56 includes a layer of tungsten facing the interior of the vacuum chamber 52 and which typically contains no more than 5 at % of elements other than tungsten to provide a source of sputtered tungsten.
A DC power source 60 negatively biases the target to about 600 to 1000 VDC with respect to the grounded vacuum chamber 52 or unillustrated grounded sidewall shield to excite a sputter working gas into a plasma. Conventionally, argon is the sputter working gas and is supplied into the vacuum chamber 52 from an argon gas source 62 through a mass flow controller 64. The target power excites the sputtering working gas into a plasma and positively charged ions of the plasma are accelerated towards the target 54 and sputter tungsten atoms from it. The density of the plasma is increased by placing in back of the target 56 a magnetron 66 having an inner magnetic pole 68 of one magnetic polarity surrounded by an outer magnetic pole 70 of the opposed magnetic polarity. The poles 68, 70 project a magnetic field into the vacuum chamber 52 parallel to the face of the target 56 to trap electrons and hence increase the plasma density and the resultant sputtering rate. To improve the sputtering uniformity and target utilization, the magnetic poles 68, 70 are asymmetric about the central axis 54 but supported on an arm 72 connected to a shaft 74 extending along the central axis 54. A motor 76 rotates the shaft 74 and hence the magnetron 66 about the central axis 54 to provide at least azimuthal uniformity.
A pedestal 80 within the vacuum chamber 52 supports a wafer 82 or other substrate in opposition to the target 56 to be coated with the tungsten sputtered from the target 56. A wafer is generally planar and circular except for alignment indicia. Optionally, an RF power source 84 biases the pedestal 80 through a capacitive coupling circuit 86. The pedestal 80 is conductive so that it acts as an electrode. The RF bias in the presence of a plasma within the vacuum chamber 52 causes a negative DC self-bias to develop on the pedestal 80 so that sputtered tungsten ions are accelerated towards the wafer 82 and their trajectories enter deep within any high aspect-ratio holes formed in the wafer 82.
The same sputter chamber 50 may be used to sputter deposit tungsten nitride (WN) in a reactive sputtering process. Nitrogen is selectively admitted into the vacuum chamber 52 from a nitrogen gas source 90 through a mass flow controller 92. The nitrogen reacts with the sputtered tungsten to form a layer of tungsten nitride on the surface of the wafer 82.
However, as the gate lengths further decrease towards the 35 nm node, the resistivity of the sputtered tungsten continues to be a problem.